disabling for Android "Vulkan Asynchronous Presentation"

src/common/host_memory.cpp

@@ -68,8 +68,8 @@ static int memfd_create(const char* name, unsigned int flags) {
 
 namespace Common {
 
-[[maybe_unused]] constexpr size_t PageAlignment = 0x1000;
-[[maybe_unused]] constexpr size_t HugePageSize = 0x200000;
+constexpr size_t PageAlignment = 0x1000;
+constexpr size_t HugePageSize = 0x200000;
 
 #ifdef _WIN32
 
@@ -692,16 +692,30 @@ private:
 
 #endif // ^^^ POSIX ^^^
 
-HostMemory::HostMemory(size_t backing_size_, size_t virtual_size_) : backing_size(backing_size_), virtual_size(virtual_size_) {
-    // Try to allocate a fastmem arena.
-    // The implementation will fail with std::bad_alloc on errors.
-    impl = std::make_unique<HostMemory::Impl>(AlignUp(backing_size, PageAlignment), AlignUp(virtual_size, PageAlignment) + HugePageSize);
-    backing_base = impl->backing_base;
-    virtual_base = impl->virtual_base;
-    if (virtual_base) {
-        // Ensure the virtual base is aligned to the L2 block size.
-        virtual_base = reinterpret_cast<u8*>(Common::AlignUp(uintptr_t(virtual_base), HugePageSize));
-        virtual_base_offset = virtual_base - impl->virtual_base;
+HostMemory::HostMemory(size_t backing_size_, size_t virtual_size_)
+    : backing_size(backing_size_), virtual_size(virtual_size_) {
+    try {
+        // Try to allocate a fastmem arena.
+        // The implementation will fail with std::bad_alloc on errors.
+        impl =
+            std::make_unique<HostMemory::Impl>(AlignUp(backing_size, PageAlignment),
+                                               AlignUp(virtual_size, PageAlignment) + HugePageSize);
+        backing_base = impl->backing_base;
+        virtual_base = impl->virtual_base;
+
+        if (virtual_base) {
+            // Ensure the virtual base is aligned to the L2 block size.
+            virtual_base = reinterpret_cast<u8*>(
+                Common::AlignUp(reinterpret_cast<uintptr_t>(virtual_base), HugePageSize));
+            virtual_base_offset = virtual_base - impl->virtual_base;
+        }
+
+    } catch (const std::bad_alloc&) {
+        LOG_CRITICAL(HW_Memory,
+                     "Fastmem unavailable, falling back to VirtualBuffer for memory allocation");
+        fallback_buffer = std::make_unique<Common::VirtualBuffer<u8>>(backing_size);
+        backing_base = fallback_buffer->data();
+        virtual_base = nullptr;
     }
 }
 

src/common/host_memory.h

@@ -1,6 +1,3 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
-// SPDX-License-Identifier: GPL-3.0-or-later
-
 // SPDX-FileCopyrightText: Copyright 2019 yuzu Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 
@@ -82,6 +79,9 @@ private:
     u8* backing_base{};
     u8* virtual_base{};
     size_t virtual_base_offset{};
+
+    // Fallback if fastmem is not supported on this platform
+    std::unique_ptr<Common::VirtualBuffer<u8>> fallback_buffer;
 };
 
 } // namespace Common

src/common/settings.h

@@ -466,7 +466,7 @@ struct Values {
                                                    true};
     SwitchableSetting<bool> async_presentation{linkage,
 #ifdef ANDROID
-                                               true,
+                                               false,
 #else
                                                false,
 #endif

src/core/arm/nce/arm_nce.cpp

@@ -391,15 +391,28 @@ const std::size_t CACHE_PAGE_SIZE = 4096;
 
 void ArmNce::ClearInstructionCache() {
 #ifdef __aarch64__
-    // Ensure all previous memory operations complete
+    // Use IC IALLU to actually invalidate L1 instruction cache
     asm volatile("dsb ish\n"
+                 "ic iallu\n"
                  "dsb ish\n"
                  "isb" ::: "memory");
 #endif
 }
 
 void ArmNce::InvalidateCacheRange(u64 addr, std::size_t size) {
-    this->ClearInstructionCache();
+#ifdef ARCHITECTURE_arm64
+    // Invalidate instruction cache for specific range instead of full flush
+    constexpr u64 cache_line_size = 64;
+    const u64 aligned_addr = addr & ~(cache_line_size - 1);
+    const u64 end_addr = (addr + size + cache_line_size - 1) & ~(cache_line_size - 1);
+
+    asm volatile("dsb ish" ::: "memory");
+    for (u64 i = aligned_addr; i < end_addr; i += cache_line_size) {
+        asm volatile("ic ivau, %0" :: "r"(i) : "memory");
+    }
+    asm volatile("dsb ish\n"
+                 "isb" ::: "memory");
+#endif
 }
 
 } // namespace Core