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Author SHA1 Message Date
PavelBARABANOV
f75d118a31 disabling for Android "Vulkan Asynchronous Presentation" 2025-12-21 20:27:15 +03:00
4 changed files with 18 additions and 4 deletions

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@@ -32,6 +32,7 @@ void SinkStream::AppendBuffer(SinkBuffer& buffer, std::span<s16> samples) {
auto yuzu_volume = Settings::Volume();
if (yuzu_volume > 1.0f)
yuzu_volume = 0.6f + 20.0f * std::log10(yuzu_volume);
yuzu_volume = std::max(yuzu_volume, 0.001f);
auto const volume = system_volume * device_volume * yuzu_volume;
if (system_channels > device_channels) {

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@@ -466,7 +466,7 @@ struct Values {
true};
SwitchableSetting<bool> async_presentation{linkage,
#ifdef ANDROID
true,
false,
#else
false,
#endif

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@@ -391,15 +391,28 @@ const std::size_t CACHE_PAGE_SIZE = 4096;
void ArmNce::ClearInstructionCache() {
#ifdef __aarch64__
// Ensure all previous memory operations complete
// Use IC IALLU to actually invalidate L1 instruction cache
asm volatile("dsb ish\n"
"ic iallu\n"
"dsb ish\n"
"isb" ::: "memory");
#endif
}
void ArmNce::InvalidateCacheRange(u64 addr, std::size_t size) {
this->ClearInstructionCache();
#ifdef ARCHITECTURE_arm64
// Invalidate instruction cache for specific range instead of full flush
constexpr u64 cache_line_size = 64;
const u64 aligned_addr = addr & ~(cache_line_size - 1);
const u64 end_addr = (addr + size + cache_line_size - 1) & ~(cache_line_size - 1);
asm volatile("dsb ish" ::: "memory");
for (u64 i = aligned_addr; i < end_addr; i += cache_line_size) {
asm volatile("ic ivau, %0" :: "r"(i) : "memory");
}
asm volatile("dsb ish\n"
"isb" ::: "memory");
#endif
}
} // namespace Core

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@@ -134,4 +134,4 @@ target_include_directories(dynarmic_tests PRIVATE . ../src)
target_compile_options(dynarmic_tests PRIVATE ${DYNARMIC_CXX_FLAGS})
target_compile_definitions(dynarmic_tests PRIVATE FMT_USE_USER_DEFINED_LITERALS=1)
add_test(NAME dynarmic_tests COMMAND dynarmic_tests --durations yes)
add_test(dynarmic_tests dynarmic_tests --durations yes)