It seems to work that way too.

src/core/arm/nce/arm_nce.cpp

@@ -390,15 +390,14 @@ const std::size_t CACHE_PAGE_SIZE = 4096;
 void ArmNce::ClearInstructionCache() {
 #ifdef __aarch64__
     // Ensure all previous memory operations complete
-    asm volatile(
-        "\tdmb ish\n"
-        "\tdsb ish\n"
-        "\tisb\n" ::: "memory");
+    asm volatile("dmb ish" ::: "memory");
+    asm volatile("dsb ish" ::: "memory");
+    asm volatile("isb" ::: "memory");
 #endif
 }
 
 void ArmNce::InvalidateCacheRange(u64 addr, std::size_t size) {
-    ClearInstructionCache();
+    this->ClearInstructionCache();
 }
 
 } // namespace Core

src/core/arm/nce/interpreter_visitor.cpp

@@ -183,16 +183,17 @@ bool InterpreterVisitor::Ordered(size_t size, bool L, bool o0, Reg Rn, Reg Rt) {
     u64 address = (Rn == Reg::SP) ? this->GetSp() : this->GetReg(Rn);
     switch (memop) {
     case MemOp::Store: {
-        std::atomic_thread_fence(std::memory_order_release);
+        std::atomic_thread_fence(std::memory_order_seq_cst);
         u64 value = this->GetReg(Rt);
         m_memory.WriteBlock(address, &value, dbytes);
+        std::atomic_thread_fence(std::memory_order_seq_cst);
         break;
     }
     case MemOp::Load: {
         u64 value = 0;
         m_memory.ReadBlock(address, &value, dbytes);
-        std::atomic_thread_fence(std::memory_order_acquire);
         this->SetReg(Rt, value);
+        std::atomic_thread_fence(std::memory_order_seq_cst);
         break;
     }
     default:

src/video_core/renderer_vulkan/vk_pipeline_cache.cpp

@@ -677,6 +677,7 @@ std::unique_ptr<GraphicsPipeline> PipelineCache::CreateGraphicsPipeline(
 
         const auto runtime_info{MakeRuntimeInfo(programs, key, program, previous_stage)};
         ConvertLegacyToGeneric(program, runtime_info);
+
         const std::vector<u32> code{EmitSPIRV(profile, runtime_info, program, binding, this->optimize_spirv_output)};
         device.SaveShader(code);
         modules[stage_index] = BuildShader(device, code);
@@ -771,6 +772,17 @@ std::unique_ptr<ComputePipeline> PipelineCache::CreateComputePipeline(
     }
 
     auto program{TranslateProgram(pools.inst, pools.block, env, cfg, host_info)};
+
+    // Adreno have lower shared memory limits (32KB)
+    // Clamp shared memory usage to device maximum to avoid validation errors
+    const u32 max_shared_memory = device.GetMaxComputeSharedMemorySize();
+    if (program.shared_memory_size > max_shared_memory) {
+        LOG_WARNING(Render_Vulkan,
+                    "Compute shader 0x{:016x} requests {}KB shared memory but device max is {}KB - clamping",
+                    key.unique_hash, program.shared_memory_size / 1024, max_shared_memory / 1024);
+        program.shared_memory_size = max_shared_memory;
+    }
+
     const std::vector<u32> code{EmitSPIRV(profile, program, this->optimize_spirv_output)};
     device.SaveShader(code);
     vk::ShaderModule spv_module{BuildShader(device, code)};