fix2

src/core/arm/nce/arm_nce.cpp

@@ -390,14 +390,15 @@ const std::size_t CACHE_PAGE_SIZE = 4096;
 void ArmNce::ClearInstructionCache() {
 #ifdef __aarch64__
     // Ensure all previous memory operations complete
-    asm volatile("dmb ish" ::: "memory");
-    asm volatile("dsb ish" ::: "memory");
-    asm volatile("isb" ::: "memory");
+    asm volatile(
+        "\tdmb ish\n"
+        "\tdsb ish\n"
+        "\tisb\n" ::: "memory");
 #endif
 }
 
 void ArmNce::InvalidateCacheRange(u64 addr, std::size_t size) {
-    this->ClearInstructionCache();
+    ClearInstructionCache();
 }
 
 } // namespace Core

src/core/arm/nce/interpreter_visitor.cpp

@@ -183,17 +183,16 @@ bool InterpreterVisitor::Ordered(size_t size, bool L, bool o0, Reg Rn, Reg Rt) {
     u64 address = (Rn == Reg::SP) ? this->GetSp() : this->GetReg(Rn);
     switch (memop) {
     case MemOp::Store: {
-        std::atomic_thread_fence(std::memory_order_seq_cst);
+        std::atomic_thread_fence(std::memory_order_release);
         u64 value = this->GetReg(Rt);
         m_memory.WriteBlock(address, &value, dbytes);
-        std::atomic_thread_fence(std::memory_order_seq_cst);
         break;
     }
     case MemOp::Load: {
         u64 value = 0;
         m_memory.ReadBlock(address, &value, dbytes);
+        std::atomic_thread_fence(std::memory_order_acquire);
         this->SetReg(Rt, value);
-        std::atomic_thread_fence(std::memory_order_seq_cst);
         break;
     }
     default: