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JitArm64_Integer: Merge subfx and subfcx

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The optimizations for subfcx introduced in #13852 also apply to subfx.
Rather than duplicating the logic, we merge the handlers, like we did
in #10120 for x86.
This commit is contained in:
Sintendo
2025-09-20 10:08:31 +02:00
parent 490615c72a
commit 419f90107d
3 changed files with 22 additions and 30 deletions
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1
Source/Core/Core/PowerPC/JitArm64/Jit.h
View File

@@ -114,7 +114,6 @@ public:
void rlwimix(UGeckoInstruction inst);
void subfex(UGeckoInstruction inst);
void subfzex(UGeckoInstruction inst);
void subfcx(UGeckoInstruction inst);
void subfic(UGeckoInstruction inst);
void addex(UGeckoInstruction inst);
void divwux(UGeckoInstruction inst);

47
Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
View File

@@ -18,15 +18,18 @@
using namespace Arm64Gen;
using namespace JitCommon;
#define CARRY_IF_NEEDED(inst_without_carry, inst_with_carry, ...) \
#define CARRY_IF_NEEDED_COND(carry, inst_without_carry, inst_with_carry, ...) \
do \
{ \
if (js.op->wantsCA) \
if ((carry) && js.op->wantsCA) \
inst_with_carry(__VA_ARGS__); \
else \
inst_without_carry(__VA_ARGS__); \
} while (0)
#define CARRY_IF_NEEDED(inst_without_carry, inst_with_carry, ...) \
CARRY_IF_NEEDED_COND(true, inst_without_carry, inst_with_carry, __VA_ARGS__)
void JitArm64::ComputeRC0(ARM64Reg reg)
{
gpr.BindCRToRegister(0, false);
@@ -1114,20 +1117,6 @@ void JitArm64::addzex(UGeckoInstruction inst)
ComputeRC0(gpr.R(d));
}
void JitArm64::subfx(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITIntegerOff);
FALLBACK_IF(inst.OE);
int a = inst.RA, b = inst.RB, d = inst.RD;
gpr.BindToRegister(d, d == a || d == b);
SUB(gpr.R(d), gpr.R(b), gpr.R(a));
if (inst.Rc)
ComputeRC0(gpr.R(d));
}
void JitArm64::subfex(UGeckoInstruction inst)
{
INSTRUCTION_START
@@ -1259,13 +1248,14 @@ void JitArm64::subfex(UGeckoInstruction inst)
ComputeRC0(gpr.R(d));
}
void JitArm64::subfcx(UGeckoInstruction inst)
void JitArm64::subfx(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITIntegerOff);
FALLBACK_IF(inst.OE);
int a = inst.RA, b = inst.RB, d = inst.RD;
const int a = inst.RA, b = inst.RB, d = inst.RD;
const bool carry = !(inst.SUBOP10 & (1 << 5));
if (gpr.IsImm(a))
{
@@ -1278,7 +1268,8 @@ void JitArm64::subfcx(UGeckoInstruction inst)
gpr.BindToRegister(d, false);
MOV(gpr.R(d), gpr.R(b));
}
ComputeCarry(true);
if (carry)
ComputeCarry(true);
if (inst.Rc)
ComputeRC0(gpr.R(d));
return;
@@ -1289,8 +1280,10 @@ void JitArm64::subfcx(UGeckoInstruction inst)
if (low_12 || high_12)
{
gpr.BindToRegister(d, d == b);
CARRY_IF_NEEDED(SUB, SUBS, gpr.R(d), gpr.R(b), high_12 ? imm >> 12 : imm, high_12);
ComputeCarry();
CARRY_IF_NEEDED_COND(carry, SUB, SUBS, gpr.R(d), gpr.R(b), high_12 ? imm >> 12 : imm,
high_12);
if (carry)
ComputeCarry();
if (inst.Rc)
ComputeRC0(gpr.R(d));
return;
@@ -1300,8 +1293,9 @@ void JitArm64::subfcx(UGeckoInstruction inst)
if (gpr.IsImm(b, 0))
{
gpr.BindToRegister(d, d == a);
CARRY_IF_NEEDED(NEG, NEGS, gpr.R(d), gpr.R(a));
ComputeCarry();
CARRY_IF_NEEDED_COND(carry, NEG, NEGS, gpr.R(d), gpr.R(a));
if (carry)
ComputeCarry();
if (inst.Rc)
ComputeRC0(gpr.R(d));
return;
@@ -1310,10 +1304,9 @@ void JitArm64::subfcx(UGeckoInstruction inst)
gpr.BindToRegister(d, d == a || d == b);
// d = b - a
CARRY_IF_NEEDED(SUB, SUBS, gpr.R(d), gpr.R(b), gpr.R(a));
ComputeCarry();
CARRY_IF_NEEDED_COND(carry, SUB, SUBS, gpr.R(d), gpr.R(b), gpr.R(a));
if (carry)
ComputeCarry();
if (inst.Rc)
ComputeRC0(gpr.R(d));
}

4
Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
View File

@@ -172,8 +172,8 @@ constexpr std::array<JitArm64OpTemplate, 107> s_table31{{
{616, &JitArm64::negx}, // negox
{40, &JitArm64::subfx}, // subfx
{552, &JitArm64::subfx}, // subfox
{8, &JitArm64::subfcx}, // subfcx
{520, &JitArm64::subfcx}, // subfcox
{8, &JitArm64::subfx}, // subfcx
{520, &JitArm64::subfx}, // subfcox
{136, &JitArm64::subfex}, // subfex
{648, &JitArm64::subfex}, // subfeox
{232, &JitArm64::subfex}, // subfmex