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[FIXUP] Partially revert "[NCE] Fix cache invalidation and signal interrupt race condition (#3063)" (#3190)

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* this fixes Jamboree and SSB

This reverts commit e3c942b209.

Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3190
Reviewed-by: Maufeat <sahyno1996@gmail.com>
Reviewed-by: MaranBr <maranbr@eden-emu.dev>
Co-authored-by: Caio Oliveira <caiooliveirafarias0@gmail.com>
Co-committed-by: Caio Oliveira <caiooliveirafarias0@gmail.com>
This commit is contained in:
Caio Oliveira
2025-12-22 02:58:40 +01:00
committed by crueter
parent bccc46a325
commit 3413fbd9da
1 changed files with 2 additions and 15 deletions
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17
src/core/arm/nce/arm_nce.cpp
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@@ -391,28 +391,15 @@ const std::size_t CACHE_PAGE_SIZE = 4096;
void ArmNce::ClearInstructionCache() { void ArmNce::ClearInstructionCache() {
#ifdef __aarch64__ #ifdef __aarch64__
// Use IC IALLU to actually invalidate L1 instruction cache // Ensure all previous memory operations complete
asm volatile("dsb ish\n" asm volatile("dsb ish\n"
"ic iallu\n"
"dsb ish\n" "dsb ish\n"
"isb" ::: "memory"); "isb" ::: "memory");
#endif #endif
} }
void ArmNce::InvalidateCacheRange(u64 addr, std::size_t size) { void ArmNce::InvalidateCacheRange(u64 addr, std::size_t size) {
#ifdef ARCHITECTURE_arm64 this->ClearInstructionCache();
// Invalidate instruction cache for specific range instead of full flush
constexpr u64 cache_line_size = 64;
const u64 aligned_addr = addr & ~(cache_line_size - 1);
const u64 end_addr = (addr + size + cache_line_size - 1) & ~(cache_line_size - 1);
asm volatile("dsb ish" ::: "memory");
for (u64 i = aligned_addr; i < end_addr; i += cache_line_size) {
asm volatile("ic ivau, %0" :: "r"(i) : "memory");
}
asm volatile("dsb ish\n"
"isb" ::: "memory");
#endif
} }
} // namespace Core } // namespace Core